1/10 february 2003 n high speed: t pd = 5.3 ns (typ.) at v cc =3v n 5v tolerant input n low power dissipation: i cc =4 m a(max.)att a =25c n input voltage level : v il =0.8,v ih =2v at v cc =3v n power down protection on inputs &outputs n symmetrical output impedance: |i oh |=i ol =4ma(min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 3.6v (1.2v data retention) n improved latch-up immunity n low noise: v olp = 0.3v (typ.) at vcc=3v description the74lvx16245isanadvancedhigh-speed cmos 16-bit bus transceiver (3-state) fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. this ic is intended for two-way asynchronous communication between data busses; the direction of data transmission is determined by dir input. the enable input g can be used to disable the device so that the busses are effectively isolated. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. all floating bus terminals during high z state must be held high or low. 74lvx16245 16-bit bus transceiver with 3-state outputs, 5v tolerant inputs order codes package tube t & r tssop 74LVX16245TTR tssop pin connection
74lvx16245 2/10 input equivalent circuit pin description truth table x : dont care z : high impedance iec logic symbols pin no symbol name and function 1 1dir directional control 2, 3, 5, 6, 8, 9, 11, 12 1b1 to 1b8 data inputs/outputs 13, 14, 16, 17, 19, 20, 22, 23 2b1 to 2b8 data inputs/outputs 24 2dir directional control 25 2g output enable input 36, 35, 33, 32, 30, 29, 27, 26 2a1 to 2a8 data inputs/outputs 47, 46, 44, 43, 41, 40, 38, 38 1a1 to 1a8 data inputs/outputs 48 1g output enable input 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0v) 7, 18, 31, 42 v cc positive supply voltage inputs function output g dir a bus b bus yn lloutputinputa=b l h input output b = a hxzzz
74lvx16245 3/10 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied recommended operating conditions 1) truth table guaranteed: 1.2 to 3.6v 1) v in from 0.8 to 2.0v symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage (dir, g ) -0.5 to +7.0 v v i/o bus i/o voltage -0.5 to v cc +0.5 v v o dc output voltage -0.5 to v cc +0.5 v i ik dc input diode current -20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 75 ma t stg storage temperature -65to+150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage (note 1) 2to3.6 v v i input voltage (dir, g ) 0to5.5 v v i/o busi/ovoltage 0tov cc v v o output voltage 0 to v cc v t op operating temperature -55to125 c dt/dv input rise and fall time (note 2) (v cc =3.0) 0to100 ns/v
74lvx16245 4/10 dc specifications ac electrical characteristics (input t r =t f =3ns) (*) voltage range is 3.3v 0.3v note 1 : parameter guaranteed by design. t solh =|t plhm -t plhn |, t sohl =|t phlm -t phln | symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 3.0 2.0 2.0 2.0 3.6 2.4 2.4 2.4 v il low level input voltage 2.0 0.5 0.5 0.5 v 3.0 0.8 0.8 0.8 3.6 0.8 0.8 0.8 v oh high level output voltage 2.0 i o =-50 m a 1.9 2.0 1.9 1.9 v 3.0 i o =-50 m a 2.9 3.0 2.9 2.9 3.0 i o =-4 ma 2.58 4.5 2.48 2.4 v ol low level output voltage 2.0 i o =50 m a 0.0 0.1 0.1 v 3.0 i o =50 m a 0.0 0.1 0.1 3.0 i o =4 m a 0.36 0.44 0.55 ioz high impedance output leakage current 5.5 v i =v ih or v il v o =v cc or gnd 0.25 2.5 2.5 m a i i input leakage current 0to 5.5 v i =5.5vorgnd 0.1 1 1 m a i cc quiescent supply current 5.5 v i =v cc or gnd 44040 m a symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time 2.7 15 5.7 9.0 1.0 10.5 1.0 10.5 ns 2.7 50 8.0 12.3 1.0 14.0 1.0 14.0 3.3 (*) 15 5.3 8.4 1.0 10.0 1.0 10.0 3.3 (*) 50 7.8 11.9 1.0 13.5 1.0 13.5 t pzl t pzh output disable time 2.7 15 r l =1k w 7.0 11.0 1.0 13.5 1.0 13.5 ns 2.7 50 r l =1k w 9.6 15.1 1.0 16.5 1.0 16.5 3.3 (*) 15 r l =1k w 6.6 10.6 1.0 12.5 1.0 12.5 3.3 (*) 50 r l =1k w 9.1 14.1 1.0 16.0 1.0 16.0 t plz t phz output enable time 2.7 50 r l =1k w 10.8 15.0 1.0 16.5 1.0 16.5 ns 3.3 (*) 50 r l =1k w 10.3 14.0 1.0 16.0 1.0 16.0 t oslh t oshl output to output skew time (note 1) 3.3 (*) 50 1.5 1.5 1.5 ns 3.3 (*) 50 1.0 1.0 1.0
74lvx16245 5/10 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /8 (per circuit) dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 3.3v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 3.3v. inputs under test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. symbol parameter test condition value unit t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 4101010pf c i/o output capacitance 8pf c pd power dissipation capacitance (note 1) 21 pf symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 3.3 c l =50pf 0.3 0.8 v v olv -0.8 -0.3 v ihd dynamic high voltage input (note 1, 3) 3.3 2.0 v v ild dynamic low voltage input (note 1, 3) 3.3 0.8 v
74lvx16245 6/10 test circuit c l =15/ 50pf or equivalent (includes jig and probe capacitance) r l =r 1 =1k w or equivalent r t =z out of pulse generator (typically 50 w waveform 1: propagation delays (f=1mhz; 50% duty cycle) test switch t plh ,t phl open t pzl ,t plz v cc t pzh ,t phz gnd
74lvx16245 7/10 waveform 2: output enable and disable time (f=1mhz; 50% duty cycle)
74lvx16245 8/10 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 d 12.4 12.6 0.488 0.496 e 8.1 bsc 0.318 bsc e1 6.0 6.2 0.236 0.244 e 0.5 bsc 0.0197 bsc k0? 8?0? 8? l 0.50 0.75 0.020 0.030 tssop48 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7065588c
74lvx16245 9/10 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.197 ao 8.7 8.9 0.343 0.350 bo 13.1 13.3 0.516 0.524 ko 1.5 1.7 0.059 0.067 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel tssop48 mechanical data
74lvx16245 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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